The present invention relates generally to the field of video signal generation. More particularly, the present invention relates to a system and method for synchronizing multiple video signals using only a vertical sync reference signal.
As monitors become less expensive, desktop PCs and workstations with multiple displays are rapidly becoming commonplace. Multiple screens can also be useful in fields such as simulation, where wraparound screens are needed for the realistic reproduction of the simulation environment. Simulation applications typically require a fast update of the image being displayed in order to present the illusion of smooth real-time motion.
Displaying real-time information on multiple screens can be technically challenging. For example, a three-channel simulation device might consist of a center screen, left screen, and a right screen. The three images should present a seamless view of the simulation environment to the observer. If the visual scene rolls, a consistent horizon line should be visible across the three channels. If, however, the video refresh of the three displays are running asynchronously, it is possible to see a discontinuity along that horizon line since each segment of the scene is displayed at different times. Therefore, for real-time or interactive applications, it is important to synchronize each of the display devices.
The pixel resolution of each of the displays may differ, but the vertical rate should be synchronized. For some applications, there is also a need to synchronize the vertical rate and phase of each of these displays to an external reference synchronization signal. In addition to scene artifacts, lack of synchronization can cause poor correlation with other system equipment such as sensor displays, motion systems, sound, etc. These anomalies can contribute to simulator sickness and reduces overall effectiveness of the simulation.
Traditional high-end simulation devices have provided a means to synchronize multiple display images via a video generator lock circuit. Video generator lock, or Genlock, generates a pixel clock locked in a predictable phase relationship to a lower frequency reference (usually the horizontal sync). In most cases, each of the video circuits to be locked run at the same frequency and the solution is straightforward using a standard line-locking phase lock loop (PLL). However, implementation becomes more difficult when two or more video circuits do not have the same line and pixel counts. With some combinations of line and pixel counts for the locked video circuits, standard PLLs cannot generate the pixel clock needed to maintain lock without adding discontinuities such as skipping some blanked pixels or lines. There are also situations where it is advantageous for all video circuits in the system to lock to an external system synchronization source that only has a vertical rate signal.
What is needed, therefore, is a system and method for synchronizing multiple video streams using a vertical rate reference sync signal. What is further needed is such a system configured to maintain low jitter while offering flexibility in choosing and line and pixel resolutions.
It would be desirable to provide a system and/or method that provides one or more of these or other advantageous features. Other features and advantages will be made apparent from the present specification. The teachings disclosed extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the aforementioned needs.